1. Field of the Invention
This invention relates generally to semiconductor structures and processes, and more particularly to an improved silicide capacitor design and its method of manufacture.
2. Description of the Prior Art
Recent advances in integrated circuit processing technology, especially in lithography and dry etching, have significantly reduced device dimensions. To improve yields and lower prices, it is, of course, desirable to reduce device dimensions as much as possible.
Dynamic RAM (Random Access Memory) technology requires the fabrication of extremely small, low leakage capacitors in each memory cell. The fundamental limits governing the minimum size of these capacitors, and hence the memory cell size, can be expressed as follows:
Minimizing the area, A, of the memory capacitor is subject to
A/t.epsilon.V.gtoreq.Q.sub.c (critical charge constraint) PA1 V/t.ltoreq.E (field strength constraint) PA1 t.gtoreq.t.sub.min (dielectric integrity constraint) PA1 t.ltoreq.A .epsilon./Q.sub.c V PA1 t.gtoreq.1/E V PA1 t.gtoreq.t.sub.min.
where t is the thickness of the capacitor dielectric; PA2 .epsilon. is the dielectric constant; PA2 V is the voltage across the capacitor; PA2 E is the maximum acceptable electric field strength; PA2 t.sub.min is the the minimum dielectric thickness such that the integrity is not jeopardized by pinholes; and PA2 Q.sub.c is the minimum charge difference needed to distinguish a stored "1" from a stored "0".
Rewriting the constraints:
The optimal solution, i.e., minimum value of A, can be written as EQU A.sub.min .epsilon./Q.sub.c V=1/E V
thus EQU A.sub.min =Q.sub.c /.epsilon.E.
This solution is optimal for all values of t greater than t.sub.min which satisfy the equation V/t=E.
With present technology for a dynamic RAM to have useful signal levels and soft-error immunity the cell capacitor needs to store about 300,000 electrons (Q.sub.c). Additionally because the capacitor dielectric must withstand the operating voltage (E), the minimum capacitor area (A.sub.min) is heavily dependent upon the dielectric material used (.epsilon.).
Prior art techniques utilize capacitor dielectrics of silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4) or a silicon depletion region. Capacitors constructed from these materials have several deficiencies. For example, they have a limited storage capacity thereby restricting the minimum size of the capacitor. Furthermore, their poor edge coverage and etching difficulties result in capacitor periphery shorting. In addition, formation of pinholes through the capacitor dielectric severly limits yield.
Another prior method utilizes tantalum pentoxide (Ta.sub.2 O.sub.5) film as the capacitor dielectric. See, for example, McLean et al., Proc. IEEE, 52, 1450 (1964). Attempts to apply tantalum pentoxide film as the storage capacitor in highly integrated dynamic MOS random access memories to form a large capacitance have been reported in Kayanagi et al., Jpn. J. Appl. Phys., 18-1, 135 (1978) and Ohta et al., IEEE Trans. Electron. Devices, ed-29, 368 (1982). Furthermore, tantalum pentoxide film is a promising material for enabling large capacitance in proposed very large scale integration devices. This is due to the exceptional dielectric characteristics of tantalum pentoxide film, as compared to other prior art dynamic RAM capacitor dielectric materials (See Table 1).
TABLE 1 __________________________________________________________________________ DRAM Capacitor Dielectric Materials Dielectric Cap size Material Constant Eb (MV/cm.sup.2) .epsilon. Eb (fC/u.sup.2) (sq u) __________________________________________________________________________ SiO.sub.2 4 10 35 4.6 Si.sub.3 N.sub.4 7 10 60 2.6 Ta.sub.2 O.sub.5 25 6-8 150 1.1 __________________________________________________________________________
As can be seen from the Table, tantalum pentoxide has a dielectric constant of about 25, and tantalum capacitors are capable of storing 2 to 3 times as much charge per unit area as prior art nitride capacitors. Accordingly, use of tantalum pentoxide as a dielectric permits a drastic reduction in capacitor area required for a dynamic RAM cell.
The use of tantalum pentoxide as the capacitor dielectric also reduces yield loss that would result from capacitor dielectric shorts such as edge shorts and pinholes, The nature of tantalum pentoxide film growth is such that the films are inherently pinhole-free and slightly thickened at the edges. This enhanced perimeter thickness reduces the likelihood of edge shorts, which are a particular problem for nitride capacitors.
Conventional tantalum pentoxide films are formed by anodic oxidation of a tantalum film in a wet solution, or, alternatively, using reactive sputtering of a metallic tantalum target. Standard MOSRAM fabrication techniques, however, require high temperature annealing (near 1000.degree. C.) after the dielectric film has been deposited. It has been determined that high temperatures (&gt;400.degree. C.) cause polycrystallization of the tantalum pentoxide film, and/or formation of pinholes through the film, creating high leakage current and rendering the film unusable as a dielectric. In a recent study by Kimura et al. ("Leakage-Current Increase in Amorphous Ta.sub.2 O.sub.5 Films Due to Pinhole Growth During Annealing Below 600.degree. C.," Journal of the Electrochemical Society, Vol. 130, No. 12, December, 1983), the authors conclude that ("all processing which follows capacitor dielectric deposition must be restricted to low temperatures. . . ")it is necessary to have a low temperature process for tantalum pentoxide film to be applied to large scale integration as a dielectric material.
In addition, it has been found that tantalum pentoxide film is similarly unstable in the presence of high electric fields, further limiting its application as a dielectric in some devices. These factors severely limit the potential application of tantalum pentoxide capacitors, and more than offset its otherwise attractive dielectric properties.